The present invention relates to a semiconductor design technology and, more particularly to a back-bias voltage generating circuit of the semiconductor device. Particularly, the invention relates to a back-bias voltage generating circuit capable of stable operation by controlling the level of a back-bias voltage to be within a predetermined range.
Most semiconductor devices headed by a dynamic random access memory (DRAM) internally provides a plurality of internal voltages, which are required to operate internal circuits in a chip, by using an internal voltage generator. The internal voltage generator generates a plurality of internal voltage signals with a plurality of voltage levels using power supply voltage (VDD) and ground voltage VSS from an external circuit.
Generally, the generation of a plurality of internal voltages includes processes to produce a reference voltage signal having a reference voltage level and to produce the internal voltage using a charge pumping or down-converting technique based on the reference voltage signal.
Here, typical internal voltages, which are generated by the charge pumping technique, are a boosted voltage VPP and a back-bias voltage VBB, and a typical internal voltage, which is generated by the down-converting technique, is a core voltage VCORE.
The core voltage VCORE is lower than the external power supply voltage VDD and is higher than a ground voltage VSS. This voltage is required to reduce power consumption in maintaining the voltage level of data, which are stored in memory cells, and to maintain a stable operation of cell transistors.
The boosted voltage VPP is higher than the external power supply voltage VDD. This voltage is required to be supplied to a word line that is connected to a gate of a cell transistor when a memory cell is accessed. This boosted voltage VPP prevents the cell data loss that is caused by the threshold voltage (Vth) of a cell transistor.
Also, the back-bias voltage VBB is lower than the external ground voltage VSS. The back-bias voltage VBB reduces the variation of the threshold voltage Vth of the cell transistor, which is caused by the body effect. Accordingly, the back-bias voltage VBB increases the stabilization of the cell transistor and reduces a channel leakage current generated in the cell transistor.
Of the internal voltages of the semiconductor device, i.e., the boosted voltage, the back-bias voltage VBB and the core voltage VCORE, the generation of the back-bias voltage VBB will be described briefly based on the charge pumping technique.
FIG. 1 is a block diagram illustrating a back-bias voltage generator of a conventional semiconductor memory device.
Referring to FIG. 1, the back-bias voltage generator includes a back-bias voltage detector 100, an oscillator 120, and a back-bias charge pump 140. The back-bias voltage detector 100 detects a back-bias voltage based on a predetermined target level. The oscillator 120 produces an oscillation signal VBB_OSC at a predetermined frequency in response to an detection signal VBB_DET of the back-bias voltage detector 100. The back-bias charge pump 140 drives a back-bias voltage output terminal by performing a charge pumping operation in response to the oscillation signal VBB_OSC of the oscillator 120.
In the conventional back-bias voltage generator of FIG. 1, the back-bias voltage detector 100 activates and outputs the detection signal VBB_DET when the voltage level at the back-bias voltage output terminal is higher than a predetermined target level (typically, −0.8V). On the contrary, when the voltage level at the back-bias voltage output terminal is lower than the predetermined target level, the back-bias voltage detector 100 deactivates the detection signal VBB_DET.
At this time, when the detection signal VBB_DET is activated, the oscillator 120 oscillates and outputs the oscillation signal VBB_OSC at a predetermined frequency. When the detection signal VBB_DET is deactivated, the oscillator 120 fixes the oscillation signal VBB_OSC to a predetermined logic level, for example, to a logic low or high level.
Furthermore, when the oscillation signal VBB_OSC which is oscillated at the predetermined frequency is inputted, the back-bias charge pump 140 conducts the voltage drop at the back-bias voltage output terminal by driving the back-bias voltage output terminal. That is, the back-bias charge pump 140 controls the back-bias voltage output terminal in order that the voltage level at the back-bias voltage output terminal is lower than the predetermined target level. On the contrary, when the oscillation signal VBB_OSC that is fixed to the predetermined logic level is inputted, the driving operation of the back-bias voltage output terminal is not carried out at back-bias charge pump 140. That is, the driving operation of the back-bias voltage output terminal is not carried out until the voltage level of the back-bias voltage output terminal is higher than the predetermined target level due to an operation of the semiconductor memory device.
As mentioned above, the semiconductor memory device produces the back-bias voltage VBB. However, the conventional back-bias voltage generator uses a method for producing the back-bias voltage VBB with a predetermined driving force, regardless of an operating mode of the semiconductor memory device, i.e., an active mode or a standby mode.
Accordingly, the driving force of the back-bias charge pump 140 is determined based on the active mode of the semiconductor memory device that makes relatively much use of the back-bias voltage VBB. That is, when the semiconductor memory device operates in the active mode, the voltage level of the back-bias voltage output terminal swings in a range of a predetermined target level.
However, when the semiconductor memory device operates in the standby mode, the usage of the back-bias voltage VBB is decreased. Accordingly, the voltage level of the back-bias voltage output terminal is much out of the predetermined target level so that there is a problem in that the voltage level is too low, because the back-bias charge pump 140 still has the driving force for the active.
If the voltage level of the back-bias voltage output terminal is much out of the predetermined target level so that the voltage level is too low continuously, the channel leakage current generated in the cell transistor of the semiconductor memory device is increased, far from being decreased. That is, there is a problem with the cell retention time, which indicates the time to maintain the data without further supplying current, to be decreased.